Intelligent Probe Test Analytics for Predicting Final Package Yield in Semiconductor Manufacturing

Abstract

Semiconductor manufacturing requires early yield prediction because package-stage failures can increase cost, delay production, and reduce device reliability. Probe testing provides useful electrical information before assembly, but its value is often limited to pass–fail screening. This article presents an intelligent probe test analytics approach for predicting final package yield from wafer-level and die-level test indicators. The study uses probe variables such as parametric response, leakage deviation, fail-bin category, wafer-level fail rate, and test-margin distance to form yield-risk features. These features are cleaned, grouped into low-, medium-, and high-risk categories, and used in supervised learning models to estimate package yield. The results show that predicted yield decreases as probe test risk increases, and the proposed analytics model gives stronger prediction accuracy than simpler models. The approach supports earlier engineering action, better lot review, and improved use of packaging resources in semiconductor manufacturing. It also improves confidence in data-driven yield control decisions.